`timescale 1ns / 1ps
 
module DATEMEM(
 
      input [31:0] addr,
 
      input [31:0] datain,
 
      input Clock,
 
      input        we,
 
        output [31:0] dataout
 
    );
 
   reg [31:0] ram [31:0];
 
   assign dataout = ram[addr[6:2]];
 
   always @ (posedge Clock) begin
 
          if (we) ram[addr[6:2]] <= datain;
 
   end
 
   integer i;
 
   initial begin
 
          for ( i = 0 ; i <= 31 ; i = i + 1) ram [i] = i * i;
 
   end   
 
endmodule